Capacitive coupling is often caused when one signal capacitively couples with another. One of the major sources of capacitive coupling (also referred to as parasitic capacitance coupling) is from the source and drain to substrate junctions of a transistor.
At low frequencies, parasitic capacitance coupling can usually be ignored, but in high frequency circuits it becomes a major problem in limiting device performance. For example, in high-frequency circuits, e.g., 5 GHz and above, parasitic capacitance coupling to the substrate limits the switching frequency. Accordingly, if the parasitic capacitance coupling can be reduced, the transistor can be switched faster and hence increase its performance. For this reason, high frequency circuits require special design techniques to improve switching and hence performance of the transistor.
Recent advances in technology have begun to address the issue of capacitive coupling. For example, these problems are being avoided by making circuits on insulating substrates (e.g., silicon dioxide or sapphire) that have a thin layer of crystalline silicon, in which the FET is fabricated. Silicon-on-Insulator (SOI) technologies are also addressing this issue. For example, SOI can reduced the capacitance at the source and drain junctions by eliminating the depletion regions extending into the substrate. However, further advances are still required as devices are scaled.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.